VDP - Video Display Processor

Overview

The VDP contains all the circuitry necessary to generate the video display. It appears to the Z80 as two I/O ports called the Data Port and the Command Port. Although the VDP has its own 16 KB of VRAM (Video RAM), the contents of which define the screen image, this cannot be directly accessed by the Z80. Instead it must use the two I/O ports to modify the VRAM and to set the various VDP operating conditions.

The VDP in SVI-318, 328 and 728 is the Texas Instruments TMS9918A or TMS9929A for PAL versions. The TMS-9929 is effectively identical to the TMS9918 functionally and only has the color video section that is different.

It has 16 colors, and four screen modes. The resolution is always 256 x 192. It also has a sprite system wich can control 32 sprites, with a maximum of four sprites on a single horizontal line.

The following I/O ports are used to communicate with the VDP.

The VDP uses a 10.738MHz crystal. It generates all required internatl clock signal. The CPU clock is supplied by the VDP and is obtained by dividing the 10.738MHz clock by 3.
 

Video Display Modes

The VDP displays an image on the screen that can best be envisioned as a set of display planes sandwiched together. Objects on planes closest to the viewer have higher priority. In case where two entities on two different planes are occupying the same spot on the screen, the entity on the higher priority plane will show at that point. For an entity on a specific plane to show through, all planes in front of that plane must be transparent at that point.

The first 32 planes each may contain a single sprite. (Sprites are pattern objects whose positions on the screen are defined by horizontal and vertical coordinates in VRAM) The areas of the Sprite Planes, outside of the sprite itself, are transparent. Since the coordinates of the sprite are in terms of pixels, the sprite can be sizes: 8 x 8 pixels, 16 x 16 pixels and 32 x 32 pixels.

Behind the Sprite Plane is the Pattern Plane. The Pattern Plane is used for textual and graphics images generated by the Text, Graphics I, Graphics II or Multicolor modes.

Behind the Pattern Plane is the backdrop, wich is larger in area than the other planes so that it forms a border around the other planes.

The last and lowest priority plane is the External Video Plane. Its image is defined by the external video input pin. The backdrop consists of a single color used for the display borders and as the default color for the active display area. The default color is stored in the VDP register 7. When the backdrop color register contains the transparent code, the backdrop automatically defaults to black if the external video mode is not selected.

The 32 Sprite Planes are used for the 32 sprites in the Multicolor and Graphics modes. They are not used in the Text mode and are automatically transparent. Each of the sprites can cover a 8x8, 16x16 or 32x32 pixel area on its plane. Any part of the plane not covered by the sprite is transparent. All or part of each sprite may also be transparent. Sprite 0 is on the outside or highest plane, and sprite 31 is on the plane immediately adjacent to Pattern Plane. Whenever a pixel in a Sprite Plane is transparent, the color of the next plane can be seen through that plane. If, however, the sprite pixel is non-transparent, the color of the lower planes are automatically replaced by the sprite color.

There is also a restriction on the number of sprites on a line. Only four sprites can be active on any horizontal line. Additional sprites on a line will be automatically made transparent for that line. Only those sprites that are active on the display will cause the coincidence flag to set. The VDP status register provides a flag bit and the number of the fifth sprite whenever this occurs.

The Pattern Plane is used in the Text, Multicolor, and Graphics modes for display of the graphic patterns of characters. Whenever a pixel on the Pattern Table is non-transparent, the backdrop color is automatically replaced by the Pattern Plane color. When a pixel in the Pattern Plane is transparent, the backdrop color can be seen through the Pattern Plane.

The VDP has four video color display modes that appear on the Pattern Plane: Graphics I mode, Graphics II mode, Text mode and MultiColor mode. Graphics I and Graphics II modes cause the Pattern Plane to be broken up into groups of 8x8 pixels, called pattern positions. Since the full image is 256x192 pixels, there are 32x34 pattern positions on the screen in the graphics mode.

In Graphics I mode, 256 possible patterns may be defined for the 768 pattern positions with two unique colors allowed for each pattern definition.

Graphics II mode provides, through a unque mapping scheme, 768 pattern definations for the 768 patterns positions. Graphics II mode also allows tge selection of two enique colors for each line of a pattern definition.  Thus, all 15 colors plus transparent may be used in a single pattern position.

In Text mode, the Pattern Plane is broken into groups of 6x8 pixels, called text positions. There are 40x24 text positions on the screen in this mode. In the Text mode, sprites do not appear on the screen and two colors are defined for the entire screen.

In Multicolor mode, the screen is broken into a grid of 64x48 positions, each of which is a 4x4 pixel. Within each position, one unique color is allowed.

The VDP registers define the base addresses for several sub-blocks within VRAM. The sub-blocks form tables which are used to produce the desired image on the screen. The Pattern Name Table, the Pattern Generator Table and the Sprite Generator Table are used to form the sprites. The contents of these tables must all be provided by the microprocessor. Animation is achieved by altering the contents of VRAM in real time.

Data port

The Data Port is used to read or write single bytes to the VRAM. The VDP possesses an internal address register pointing to a location in the VRAM. Reading the Data Port will input the byte from this VRAM location while writing to the Data Port will store a byte there. After a read or write the address register is automatically incremented to point to the next VRAM location. Sequential bytes can be accessed simply by continuous reads or writes to the Data Port.
 

Command port

The Command Port is used for three purposes:

• To set up the Data Port address register.
• To read the VDP Status Register.
• To write to one of the VDP Registers.

Address Register

The Data Port address register must be set up in different ways depending on whether the subsequent access is to be a read or a write. The address register can be set to any value from 0000H to 3FFFH by first writing the LSB (Least Significant Byte) and then the MSB (Most Significant Byte) to the Command Port. Bits 6 and 7 of the MSB are used by the VDP to determine whether the address register is being set up for subsequent reads or writes as follows:

Read ³ xxxxxxxx ³ 00xxxxxx ³

Write ³ xxxxxxxx ³ 01xxxxxx ³

It is important that no other accesses are made to the VDP in between writing the LSB and the MSB as this will upset its synchronization. The ROM interrupt handler is continuously reading the VDP Status Register as a background task so interrupts should be disabled as necessary.
 

VDP Status Register

Reading the Command Port will input the contents of the VDP Status Register. This contains various flags as below:
 

7 6 5 4 3 2 1 0
³ F ³ 5S ³ C ³ Fifth Sprite Number ³
³Flag³Flag³Flag³ ³

The Fifth Sprite Number bits contain the number (0 to 31) of the sprite triggering the Fifth Sprite Flag.

The Coincidence Flag is normally 0 but is set to 1 if any sprites have one or more overlapping pixels. Reading the Status Register will reset this flag to a 0. Note that coincidence is only checked as each pixel is generated during a video frame, on a PAL machine this is every 20 ms. If fast moving sprites pass over each other between checks then no coincidence will be flagged.

The Fifth Sprite Flag is normally 0 but is set to 1 when there are more than four sprites on any pixel line. Reading the Status Register will reset this flag to a 0.

The Frame Flag is normally 0 but is set to a 1 at the end of the last active line of the video frame. For PAL machines with a 50 Hz frame rate this will occur every 20 ms. Reading the Status register will reset this flag to a 0. There is an associated output signal from the VDP which generates Z80 interrupts at the same rate, this drives the ROM interrupt handler.
 

VDP Mode Registers

The VDP has eight write-only registers, numbered 0 to 7, which control its general operation. A particular register is set by first writing a data byte then a register selection byte to the Command Port. The register selection byte contains the register number in the lower three bits: 10000RRR. As the Mode Registers are write-only, and cannot be read. In an MSX machine maintains the ROM an exact copy of the eight registers in the Workspace Area of RAM. Using the MSX ROM standard routines for VDP functions ensures that this register image is correctly updated.
 

Register 0

Register 1

The M1 and M2 bits determine the VDP operating mode in conjunction with the M3 bit from Register 0.

Register 2

Register 2 defines the starting address of the Name Table in the VDP VRAM. The four available bits only specify positions 00BB BB00 0000 0000 of the full address so register contents of 0FH would result in a base address of 3C00H.

This register contains bits 13 through 10 of the pattern name table. You can calculate the pattern name table address by multiplying the value of this register by 400H (1024).
 

Register 3

Register 3 defines the starting address of the Color Table in the VDP VRAM. The eight available bits only specify positions 00BB BBBB BB00 0000 of the full address so register contents of FFH would result in a base address of 3FC0H. In Graphics Mode only bit 7 is effective thus offering a base of 0000H or 2000H. Bits 0 to 6 must be 1.

This register contain bits 13 through 6 of the pattern Color table. You can calculate the pattern Color table address by multiplying the value of this register by 40h (64). In screen mode 2, this register has a different function.
 

Register 4

Register 4 defines the starting address of the Character Pattern Table in the VDP VRAM. The three available bits only specify positions 00BB B000 0000 0000 of the full address so register contents of 07H would result in a base address of 3800H. In Graphics Mode only bit 2 is effective thus offering a base of 0000H or 2000H. Bits 0 and 1 must be 1.

This register contain bits 13 through 11 of the pattern generator table. You can calculate the pattern table address by multiplying the value of this register by 200H (512). In screen mode 2, this register has a different function.
 

Register 5

Register 5 defines the starting address of the Sprite Attribute Table in the VDP VRAM. The seven available bits only specify positions 00BB BBBB B000 0000 of the full address so register contents of 7FH would result in a base address of 3F80H.

This register contain bits 13 through 7 of the sprite attribute table. You can calculate the sprite attribute table address by multiplying the value of this register by 80H (128).
 

Register 6

Register 6 defines the starting address of the Sprite Pattern Table in the VDP VRAM. The three available bits only specify positions 00BB B000 0000 0000 of the full address so register contents of 07H would result in a base address of 3800H.

This register contain bits 13 through 11 of the sprite pattern generator table. You can calculate the sprite pattern table address by multiplying the value of this register by 200h (512).
 

Register 7

The Border Color bits determine the Color of the region surrounding the active video area in all four VDP modes. They also determine the Color of all 0 pixels on the screen in 40x24 Text Mode. Note that the border region actually extends across the entire screen but will only become visible in the active area if the overlying pixel is transparent.

The Text Color 1 bits determine the Color of all 1 pixels in 40x24 Text Mode. They have no effect in the other three modes where greater flexibility is provided through the use of the Color Table. The VDP Color codes are:

 

0 Transparent	4 Dark Blue	 8 Red		12 Dark Green
1 Black 	5 Light Blue	 9 Bright Red	13 Magenta
2 Green		6 Dark Red	10 Yellow	14 Grey
3 Light Green	7 Cyan		11 Light Yellow 15 White

Screen Modes

The VDP has four operating modes, each one offering a slightly different set of capabilities. The Graphics Mode is capable of adequately performing all the functions of the other modes with only minor reservations.

An added difficulty in using the VDP arises because insufficient allowance was made in its design for the overscanning used by most televisions. The resulting loss of
characters at the screen edges has forced all the video-related MSX software into being based on peculiar screen sizes. PAL machines normally use only the central thirty-seven characters available in 40x24 Text Mode. Japanese machines, with NTSC (National Television Standards Committee) video outputs, use the
central thirty-nine characters.

The central element in the VDP, from the programmer's point of view, is the Name Table. This is a simple list of single- byte character codes held in VRAM. It is 960 bytes long in 40x24 Text Mode, 768 bytes long in 32x24 Text Mode, Graphics Mode and MultiColor Mode. Each position in the Name Table corresponds to a particular location on the screen.

During a video frame the VDP will sequentially read every character code from the Name Table, starting at the base. As each character code is read the corresponding 8x8 pattern of pixels is looked up in the Character Pattern Table and displayed on the screen. The appearance of the screen can thus
be modified by either changing the character codes in the Name Table or the pixel patterns in the Character Pattern Table.

Note that the VDP has no hardware cursor facility, if one is required it must be software generated.
 

Communication with VRAM

You must use an internal register in the VDP to read or write data. This register is used as adressregister, and decides where data will be written or read. Because the VDP can adress 16KB VRAM, the register is 14 bits (2 * 14 = 16384). To set the read/write address, write it to port 1 (I/O port 99h on the MSX and 81h for SVI-328). You must write two bytes (totaly 16 bits) to the VDP. The extra 2 bits are used to decide if it's a read or write operation to VRAM, and also if it's a register write.
 

Registers Overview

Registers 0 through 7 can only be written to, while register 8 can only be read.
 

Register 8

This is the status register.

INT

This bit is high when the VDP is requesting a INT of the Z80. This bit is reset after when this register is read. This will also stop the INT request (otherwise the Z80 will only process interrupts).

5S

High if somewhere an illegal sprite (=fifth sprite on a line) occurred.

C

High if a sprite collision (=overlapped sprites) occurred.

FS

fifth sprite number. Sprite attribute table number of first illegal sprite. Only valid of 5S is set.
 

Screen modes

There are four screen modes.
 

Screen Mode 0

In this text mode, the sprite system is disabled. Also, the pattern Color table is not used.

Patterns are area of 6 x 8 pixels. There are 256 patterns stored in the pattern table. Each pattern consists of 8 bytes. The last two bits of each byte are ignored.

The screen has 40 x 24 entries. The resolution is (40 * 6 = 240) x (24 * 8 = 192) pixels. Thus, the pattern name table contains 40 x 24 = 960 bytes. The first byte of the pattern name table is the name (=pattern number) of the top left pattern, the second the one the one on the left of it. To calculate the address in VRAM of the pattern, use this formula:

address = pattern generator table address + 8 * pattern name

The screen has the Color of the backdrop (BD in register 7), and the text of the text Color (TC in register 7).
 

Screen Mode 1

In this text mode, the sprite system is active. All the tables are used.

The full length of the pattern bytes are used (8 x 8 pixels). Each pattern has a thingy.
 

Sprites
 

Controlling the VDP

The VDP is controlled through 2 I/O ports, which both can be read and written to.
 

Writing / reading VRAM

Dispite what the manuals say, there is only one address the VDP uses for reading and writing.

To set the read/write address, write it to port 1 (I/O port 99h on the MSX). You must write two bytes:

What happens next depends on bit 6 of the second byte:

Now you can read and write data to and from the VRAM by reading and writing to port 0 (I/O port 98h on the MSX)

Note that the address raps around at beyond 3FFFh to 0.
 

Writing / reading registers

If you read port 1 (I/O port 99h), you'll get the value of register 8.

To write to a register, write the following values to port 1 (I/O port 99h):

Where V is the value and R the register. Actually, when bit 7 of the second byte is high, bit 6 through bit 3 are ignored.

Please note that to maintain compatibility with the V9938 and V9958, you must set all the unused/ignored bits to zero in the register values and in the second byte.
 

Pairing Problems

As you've probably seem, when you write to port 1, you always do it in packets of two bytes.
But what happens if an interrupt occurs in your program, when you've written the first byte but not the second ? If the interrupt program attempts to change an register or something like that, it'll surely screw things up. That's why you must always disable interrupts before writing your data to port 1.

Another weird phoneme is this: when you're in MSX BASIC, type the following:

OUT (&H99),0

You'd expect things to be screwed up severely, but it doesn't happen. What does ?

I have found the following explanation: The VDP has a flag which is low if it is expecting a first byte of a packet, and high when its expecting the second byte.
But every time any VDP port is read or written to, the flag is reset. (except, of course, when it's a packet written to port 1.)
 

Interrupts

The VDP provides the only interrupt in the MSX system. It is issued every time the screen is sent to the TV. (that is, 50Hz on a European machine (PAL) and 60Hz on any reasonable machine (NTSC).

I have found the following rules:

1. Bit 7 of register 8 gets set at the end of the display of the screen; After the last line of the screen is displayed, before the bottom border.
2. Bit 7 of register 8 can be reset by reading register 8. The bit is reset after reading it.
3. Only if bit 7 of register 8 and bit 5 register 1 are set, the INT line is low (interrupt request).

No value is put on the data bus when the interrupt is acknowledged by the Z80. That's why it seems there's FFh on the data bus, making IM 0 behave the same as IM 1. (FFh = RST 38H)
 

VRAM Adresses

SCREEN 0 (Text mode, 40 column):

SCREEN 1 (Colored text mode, 32 column):

SCREEN 2 (256*192 Graphics mode):

SCREEN 3 (4x4 pixel blocks/MultiColor mode):

Sources of this document:
The Service & Technical Manual for SVI 318/382
Sean Young's MSX Net
The MSX Red Book